git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 1af55c553f3b793667e8adf834e1e59deb23d8c0 Mon Sep 17 00:00:00 2001
   2 From: Jonathan Bell <jonathan@raspberrypi.com>
   3 Date: Tue, 15 Apr 2025 14:19:31 +0100
   4 Subject: [PATCH] PCI: quirks: work around VL805 firmware ASPM meddling
   5
   6 Certain versions of the VL805 firmware manipulate the endpoint Link
   7 Control register to toggle ASPM on/off based on workload, but these
   8 versions also report 0 in the Device Capability Acceptable Latency field
   9 leaving the RC with ASPM disabled.
  10
  11 As it turns out, this EP has a broken L0s implementation so a) override
  12 L1 latency to a sensible value and b) mask L0s.
  13
  14 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  15 ---
  16  drivers/pci/quirks.c | 16 ++++++++++++++++
  17  1 file changed, 16 insertions(+)
  18
  19 --- a/drivers/pci/quirks.c
  20 +++ b/drivers/pci/quirks.c
  21 @@ -6255,6 +6255,22 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
  22  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
  23  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
  24  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
  25 +
  26 +/*
  27 + * VL805 firmware can report 0 in the L0s/L1 Acceptable Latency fields.
  28 + * This is shorter than its own exit latency so ASPM for the link partner
  29 + * never gets enabled (but firmware toggles EP L1/L0s enable internally).
  30 + * However, L0s is flaky so explicitly disable it.
  31 + */
  32 +static void vl805_aspm_fixup(struct pci_dev *dev)
  33 +{
  34 +       dev->devcap &= ~PCI_EXP_DEVCAP_L1;
  35 +       /* Set to own exit latency + 1 */
  36 +       dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 5);
  37 +       pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
  38 +       pci_info(dev, "ASPM: VL805 fixup applied\n");
  39 +}
  40 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, 0x3483, vl805_aspm_fixup);
  41  #endif
  42
  43  #ifdef CONFIG_PCIE_DPC